1. Technical Field
The present invention relates in general to a system and method for regulating voltage to an integrated circuit contained on a semiconductor substrate. In particular, the present invention relates to a system and method for regulating voltage to an integrated circuit in response to measured physical conditions of the integrated circuit itself.
2. Description of the Related Art
The performance of integrated circuits varies during the manufacturing process. Traditionally, these integrated circuits, which are manufactured on semiconductor substrate wafers, are tested and graded upon manufacture completion to determine their performance. Upon being graded, the semiconductor substrates are packaged and sold based on this measure performance. This grading details predicted performance for a specified single voltage to be provided to the integrated circuit for all operating conditions.
The integrated circuit that marginally fails to meet the performance criteria is typically discarded, even though it is fully functional without any defect. This results in yield loss. One way to marginally increase the performance of an integrated circuit is to increase the nominal operating voltage applied to it. So to ensure minimum yield loss due to underperforming integrated circuit samples, they are packaged with a higher than nominal voltage specification marked on the package itself. However, this test for performance is done at a single operating point, i.e. at a fixed temperature and given process, a measurement is made to find out what is the voltage required to attain the minimum performance criteria. In a system though, the temperature and voltages are not constant, so to guard against these variations, a voltage even higher than that needed to achieve minimum performance criteria is actually stamped on the package as the nominal voltage.
Also, calibration of individual integrated samples takes up more test time that increases cost. In such a static test method, since the power supply voltage is set at wafer based on single operating point, the opportunity to reduce power dynamically is lost.
Therefore, there is no provision made for responding to changing operating system conditions of the integrated circuit after it has been graded and packaged.